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echo "Compiling Core Verilog UNISIM/Behavioral model"
vlogcomp -work work ..\\..\\..\\wr_fifo.v
vhpcomp -work work ..\\..\\example_design\\wr_fifo_exdes.vhd

echo "Compiling Test Bench Files"
vhpcomp -work work ..\\wr_fifo_pkg.vhd
vhpcomp -work work ..\\wr_fifo_rng.vhd 
vhpcomp -work work ..\\wr_fifo_dgen.vhd
vhpcomp -work work ..\\wr_fifo_dverif.vhd
vhpcomp -work work ..\\wr_fifo_pctrl.vhd 
vhpcomp -work work ..\\wr_fifo_synth.vhd 
vhpcomp -work work ..\\wr_fifo_tb.vhd

vlogcomp -work work $XILINX\\verilog\\src\\glbl.v
fuse work.wr_fifo_tb work.glbl -L xilinxcorelib_ver -L unisims_ver -o wr_fifo_tb.exe

.\\wr_fifo_tb.exe -gui -tclbatch .\\wave_isim.tcl
